The present invention relates in general to integrated circuits, and in particular to improved method and circuitry for converting a differential logic signal of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic, to single-ended logic signal employed in standard CMOS logic.
Converting signals from C3MOS format which is differential in nature to standard CMOS format which is single-ended with rail-to-rail amplitude is a difficult operation. Most conversion circuits require careful optimization to “shape” the single-ended rail-to-rail signal. FIG. 1 depicts a conventional converter circuit with a conventional differential stage 100 that receives a differential signal Vin+/Vin−. Two optimized CMOS inverters 102 and 104 made up of transistors with skewed channel width to length W/L ratios, shape the output signal of differential stage 100. The rail-to-tail CMOS signal is obtained at output VOUT.
There are a number of disadvantages associated with this common signal level conversion technique. The two additional inverters (102 and 104) introduce long delays that may become unacceptable for ultra high speed applications such as those using C3MOS logic. Further, the delay tends to be highly variant with process corners and temperature. Moreover, the delay for the high-to-low transition is typically not equal to the delay for the low-to-high transition in the optimized inverters. This causes timing problems and, for clock signals, duty cycles deviating from 50%. Other drawbacks of most CMOS differential to single-ended converters are caused by the use of p-channel MOS (or PMOS) transistors. PMOS transistors are inherently as much as three to four times slower than NMOS transistors, and therefore aside from problems such as duty cycle distortion that is caused by this mismatch in speed, tend to slow down the overall operation of the converter circuit. Moreover, when used as load devices (as is often the case in CMOS level converter circuits), PMOS transistors introduce additional parasitic capacitance that further slows down certain internal nodes of the circuit.
There is therefore a need for differential to single ended signal level converters that operate effectively at very high speeds.